Rail-To-Rail Output Op-Amp Design with Negative Miller Capacitance Compensation

In this paper, a two-stage op-amp design is considered using both Miller and negative Miller compensation techniques. The first op-amp design uses Miller compensation around the second amplification stage, whilst the second op-amp design uses negative Miller compensation around the first stage and Miller compensation around the second amplification stage. The aims of this work were to compare the gain and phase margins obtained using the different compensation techniques and identify the ability to choose either compensation technique based on a particular set of design requirements. The two op-amp designs created are based on the same two-stage rail-to-rail output CMOS op-amp architecture where the first stage of the op-amp consists of differential input and cascode circuits, and the second stage is a class AB amplifier. The op-amps have been designed using a 0.35mm CMOS fabrication process

The Development of an Online Support Tool for the Teaching and Learning of the IEEE Standard 1500 for Embedded Core-based Integrated Circuits

In this paper, an online education tool for assisting the teaching and learning of the IEEE 1500 standard testability method, used to support the testing of complex system-on-a-chip (SoC) integrated circuits (ICs), is developed and presented. The tool is an Internet browser based tool that supports the ability to investigate key aspects of the standard and its application to embedded core-based IC designs. The tool allows the user to create VHDL descriptions of both the test circuitry and the function circuitry via the Internet browser interface. The key considerations for developing this tool were to provide a computer based learning tool to support the teaching and learning of the standard and its application. This paper is an extended version of a paper presented at the EDUCON 2012 conference in April 2012

Horizontal diversity in test generation for high fault coverage

Determination of the most appropriate test set is critical for high fault coverage in testing of digital integrated circuits. Among black-box approaches, random testing is popular due to its simplicity and cost effectiveness. An extension to random testing is antirandom that improves fault detection by maximizing the distance of every subsequent test pattern from the set of previously applied test patterns. Antirandom testing uses total Hamming distance and total cartesian distance as distance metrics to maximize diversity in the testing sequence. However, the algorithm for the antirandom test set generation has two major issues. Firstly, there is no selection criteria defined when more than one test pattern candidates have the same maximum total Hamming distance and total cartesian distance. Secondly, determination of total Hamming distance and total Cartesian distance is computational intensive as it is a summation of individual Hamming distances and cartesian distances with all the previously selected test patterns. In this paper, two-dimensional Hamming distance is proposed to address the first issue. A novel concept of horizontal Hamming distance is introduced, which acts as a third criterion for test pattern selection. Fault simulations on ISCAS’85 and ISCAS’89 benchmark circuits have shown that employing horizontal Hamming distance improves the effectiveness of pure antirandom in terms of fault coverage. Additionally, an alternative method for total Hamming distance calculations is proposed to reduce the computational intensity. The proposed method avoids summation of individual Hamming distances by keeping track of number of 0s and 1s applied at each inputs. As a result, up to 90% of the computations are reduced

Multiple controlled antirandom testing (MCAT) for high fault coverage in a black box environment

Among the black-box approaches to digital circuit testing, Random testing is popular due to its simplicity and cost effectiveness. Unfortunately, available evidences suggest that Random testing is equipped with a number of redundant patterns that increase test length without signi cantly raising the fault coverage. An extension to Random testing is Antirandom that removes redundancy by introducing a divergent pattern with every subsequent test pattern selection. A divergent pattern is induced by maximizing the Hamming distance and Cartesian distance of every subsequent test pattern from the set of previously applied test patterns. However, an enumeration of input combinations is required for the selection of a divergent pattern. Therefore, selection of a divergent pattern from all input combinations restricts the scalability of an Antirandom test pattern generation. One of the recently considered approaches is the stacking of locally optimized short sequences to generate a complete test sequence. Locally optimized short sequences originate from randomly chosen patterns instead of divergent patterns to avoid enumeration of input space. Seeding of random patterns for short sequences affects global diversity of the generated test sequence and hence, fault coverage is compromised. Therefore, this paper rstly proposes a tree traversal search based selection of divergent patterns that eliminates the search space. Ease in divergent pattern selection is used to generate optimal short sequences for divergent patterns instead of random patterns. Consequently, Multiple Controlled Antirandom Tests (MCATs) are generated that maximize distance between locally optimal short sequences to elevate the fault coverage. Fault simulation results on both ISCAS'85 and ISCAS'89 benchmark circuits prove the scalability and effectiveness of the proposed approach. Moreover, the comparison shows that up to 12% of fault coverage is improved as a result of proposed MCAT test pattern generation